POWER: Loss of Sony Playstation Platform

[Sony Playstation 3]

POWER: Loss of Sony PlayStation Platform

The Market Leaders:
Sun Microsystems introduced the RISC architecture SPARC in mid 1987. SPARC was registered as trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC architecture, manage SPARC trademarks, and provide conformance testing. Sun produced their systems on OpenFirmware, releasing it to the IEEE for standardization. SPARC found it's home on workstations, spread to servers, and even to embedded systems such as the Sun Ray in the late 1990's.


[IBM POWER5 Multi-Chip Module]

The Rise of POWER:
IBM produced the POWER architecture, an expensive multi-chip module which provided for outstanding performance at low volumes. Apple, IBM, Motorola, and decided October 2, 1991 to co-develop the POWER platform to expand the ecosystem for RISC processors under the AIM Alliance - to produce a single silicon chip high-volume RISC platform called PowerPC.

The Common Hardware Reference Platform (CHRP) for PowerPC was produced in 1994. CHRP platforms would require IEEE OpenFirmware (created by Sun) in 1995. To expand the POWER ecosystem, the "power.org" site was founded in 2004 by IBM, 15 other companies joined as members, nearly 20 years after SPARC. In 2006, the Sony Playstation released the PlayStation 3, under POWER architecture, expanding POWER into the gaming/entertainment sector.


SPARC Marches On:
In the 2000's, SPARC was no longer being used in the Sun Ray, but multiple vendors continue to produce SPARC processors. SPARC is an open specification, not a proprietary architecture, leaving multiple sources for this RISC processor. To continue to make this point, Sun Microsystems completely open-sourced their UltraSPARC T1 CPU in 2006, making SPARC it freely available for any manufacturer to produce - referring the architecture to OpenSPARC.

Fujitsu releases high-performance 8 core SPARC64 VIIIfx in 2009. The 16 core SPARC T3 was released by SUN/Oracle in 2010. Fujitsu releases another 8 core SPARC64 VII+ in 2010. Russia releases MCST-4R in 2010. Oracle released the 8 core SPARC T4 in 2011. Fujitsu is releasing SPARC64 IXfx in 2012. Oracle is projected to release the SPARC T5 in 2012.


The Decline of IBM POWER:
Apple abandoned PowerPC for Intel in 2006, leaving IBM POWER without a desktop partner. Sony is rumored to discontinue use of IBM POWER for their gaming consoles in the PlayStation 4, starting the decline of POWER in the gaming market. POWER7+ from IBM is now nearly a half-year late and IBM has still not delivered as of March 2012.

Recent Links: 2011-05-29 until 2011-06-04

Recent Links: 2011-05-29 until 2011-06-04

Some interesting articles published related to network management platforms.

[htmlpdf] - 2011-06-03 - SPARC M8000/Oracle 11g Beats IBM POWER7 on TPC-H @1000GB Benchmark
[htmlpdf] - 2011-06-02 - Solaris installation on a SPARC T3 from a remote CDROM ISO
[htmlpdf] - 2011-03-25 - SPARC M9000/Oracle 11g Delivers World Record Single Server TPC-H @3000GB Result
[htmlpdf] - 2010-07-26 - Adding a hard drive for /export/home under ZFS
[htmlpdf] - 2010-02-01 - NFS Tuning for HPC Streaming Applications
[htmlpdf] - 2010-01-21 - Graphing Solaris Performance Stats with gnuplot

IBM Power 7 and eDRAM Cache

IBM Power 7 and eDRAM Cache

Welcome IBM to the world of 64 Bit Octal-Core Computing!

On February 8th, 2010, Timothy Prickett Morgan wrote about the IBM Power 7 chip launch in The Register, "Sparc T 64-threaded T2 and T2+... quad-core, eight-threaded Tukwilas... the Power7 chip has 32 threads"'

It is nice to see the trail which first generation OpenSPARC T1 had blazed with 32 threads is being followed by IBM Power and Intel Itanium, both applying different technology to compete with Sun's second and second and third generation 64 threaded OpenSPARC processors.

Possible Architecture Trade-offs to eDRAM in Cache

Timothy Prickett Morgan also wrote, "The effect of this eDRAM on the Power7 design, and its performance, is two-fold. First, by adding the L3 cache onto the chip..."

The use of embedded DRAM, to reduce transistors, squeeze more cores, and reduce latency was a great idea, even with the refresh logic added onto the chip!

Every benefit comes with a drawbacks. The discourse on possible trade-offs have been silent, which confuses me from the media.

The use of Static RAM has been traditionally beneficial to the chip manufacturers, since they could get fast and regular access to the memory cells, without having to wait for a slow refresh signal to propagate across the RAM. It is interesting that no one (and I mean NO ONE) is talking about the impact of performance for the CPU cores needing to wait for refresh on the eDRAM.

I wonder what the ratio of performance hit to reduction in latency was in moving to eDRAM?

Multi-Ported Static RAM allows for fast (simultaneous) access from multiple cores into cache. With multi-process heavy workloads, where data in the cache may not be simultaneously accessed from different cores or hardware strands, eDRAM may be a good fit. With software multi-threaded heavy workloads, where the data in the cache will be accessed simultaneously by multiple cores and hardware strands, eDRAM may suffer in comparison to multi-ported SDRAM due to excessive inefficient re-loads from main memory and inefficient sharing.

I wonder what the ratio of benefit to performance hit in throughput for moving to eDRAM was in comparison under various real-world workloads where multi-threaded applications need to share the instructions & data in the cache?

I wonder if the performance of eDRAM will be as linear as SDRAM, as the processors get loaded up? (This reminds me of the Intel 50MHz 80486 vs Intel 66Mhz (33MHz bus) 80486 tradeoff from years past...)

Connection to Network Management

Network Management traditionally deals with extremely highly threaded workloads. Managing tens of thousands of devices with hundreds of thousands of managed resources often requires thousands of threads in a single process with very regular (1-5 minute) polling intervals required tremendous throughput.

The use of Power 7 in these types of managed device facing highly threaded workloads is yet to be measured - it may be one of the most fabulous chips on the market, or it may be mediocre, for the network management space. Power is not a substantial player in the Network Management world, so I would not really expect engineers to tune the CPU for this type of workload.

I would expect that engineers tuned Power for the Database market. Network Management does require long term storage requirements of data, so this may be a very good back-end platform.

Conclusion

The move to eDRAM is very interesting by IBM, almost as interesting as OpenSPARC moving to highly threaded octal cores many years ago.

Will other vendors emulate IBM in the move to eDRAM cache, the same way IBM, Intel, and AMD are moving to 64 bit octal-core as OpenSPARC did years ago?

U P D A T E ! ! !

Another article has come out to discuss the use of eDRAM by IBM.

First in the chain is the 32KB L1 data cache, which has seen its latency cut in half, from four cycles in the POWER6 to two cycles in POWER7. Then there's the 256KB L2, the latency of which has dropped from 26 cycles in POWER6 to eight cycles in POWER7—that's quite a reduction, and will help greatly to mitigate the impact of the shared L3's increased latency.

The POWER7's L3 is its most unique feature, and, at 32MB, it's positively gigantic. IBM was able to cram such a large L3 onto the chip by making it out of embedded DRAM (eDRAM) instead of the usual SRAM. This decision cost the cache a few cycles of latency