Wednesday, September 28, 2011

SPARC T4: Launched 2011-09-26

Link
[Oracle SPARC T4 Processor]

SPARC T4: Launched 2011-09-26


Product Launch

The Register covered the T4 product launch in an article as well as the Oracle's SPARC SuperCluster in an additional article. The writer was kind enough to include images of the new systems being released based upon the new SPARC T4 silicon.

A simple PDF data sheet on the new Oracle SPARC T4 processor is available on Oracle's web site. On Monday, September 26, 2010 - a presentation and product launch was conducted. The Event Replay is available on-line, but some of the highlights are as follows.


SPARC T4 Announcement

Some features outlined included:
  • high throughput: 8 cores, 8 threads per core
  • high thread performance: clock rate: 2.85GHz and 3.00 GHz.
  • high-thread performance: single thread can use whole core
  • high thread performance: Out of Order execution
  • 4x on-chip DDR3 Memory Controller Channels
  • 2x on-chip 10GigE networking
  • 2x on-chip x8 PCIe 2nd generation I/O interfaces
  • 18 on-chip crypto engines


Price/Performance Comparison

Some price/performance comparisons were made between a T4-4 cluster and IBM POWER 7 system.



2010 Roadmap Reminder

The market was reminded of the 2010 SPARC processor road map and how other vendors refused to release a public road map.

IBM recently released a historical road map with no dates for POWER, but it seem they might be behind.



2011 Roadmap Prediction

Oracle illustrated how SPARC is beating their road map:
  • New T4 processor in advanced customer installations today
  • New T4 processor shipping today for normal customers
  • New T5? processor for 2012, delivery projected 6-12 months early
  • New T6? processor for 2013


2012 SPARC T5?

Details for the next processor, SPARC T5? scheduled to arrive next year in 2012, revealed.

On-Chip Enhancements
  • More crypto enhancements
  • Oracle RDBMS "numbers" acceleration
  • Hardware Decompression (I requested this a few years back!)
  • Memory Versioning (is this Transactional Memory?)
  • Low Latency Clustering
Performance Enhancements
  • Higher core clock rate
  • Multiple pipelines per core
  • More Cores per Socket
  • Larger chip caches
  • More memory bandwidth

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